Intel has unveiled the Silverton platform at the Intel Developer Forum in San Francisco.

The prototype promises significant power savings by powering down components such as the graphics processor or memory when the system is idle.

Cutting down on power consumption is the logical next step in the platform's development. As Intel crafts more power-efficient processors, the platform starts taking a larger chunk of the overall power, Intel's chief technology officer Justin Rattner argued in an opening keynote at IDF.

"The potential of managing power on the platform level is really great," he told delegates.

The breakdown in power consumption between the processor and the platform in current-generation systems is about 50-50. Intel's new power efficient processors move that to roughly 33-67, Rattner claimed.

Intel unveiled its new micro-architecture for processors at the last IDF, saying that it would base the forthcoming desktop and server chips on the power efficient Banias architecture in the Pentium M.

In his keynote Rattner officially presented this new Core micro-architecture, which had remained unnamed until now.

Rattner highlighted the micro-architecture's Wide Dynamic Execution technology which allows it execute up to four instructions in a single chip cycle, limiting the number of calculations that a chip has to perform.

A technology dubbed Macro Fusion combines two instructions into one, while the new MMS technology delivers improved processing of multimedia such as audio, video and digital photos.