AMD is preparing to ship its quad-core server chips in volume, following setbacks the company encountered after the official launch in September 2007. But despite the delay, the chip maker is still confident it can maintain market share against rival Intel, which has been pursuing an aggressive introduction of multi-core server chips of its own.

The first quad-core AMD Opteron parts, codenamed Barcelona, were found to have an issue that affected the translation look-aside buffer (TLB) in the L3 cache shared among all the cores on the chip. Consequently, supply was restricted until the company could get a fix validated and into the chips coming off the production line.

“We had already started shipping, when we found an erratum using our internal automated pattern checking processes. ­ No users have reported seeing any problems,” said Randy Allen, vice president of AMD’s server and workstation division.

The problem, although rare, might have caused systems to crash. This would have been unacceptable to many of the enterprise customers expected to invest in servers based on the quad-core Opteron, so AMD took the decision to interrupt volume production of the chips.

“We decided to delay a quarter, which is what happens if you have to make a change in the silicon,” said Allen. Coming up with a fix was easy, but this then had to be put through all the quality control processes before production could be restarted using the new design, he explained.

“We have taken a lot of criticism over the delays, but partners and customers appreciate that we have taken the trouble to fix this issue,” Allen said.

The first systems with the new B3 stepping of the quad-core Opteron will be available from April, with more vendors, such as HP, following in May and June, according to AMD.

Such a slip-up ought to have proven costly to AMD, but the company claims not to have suffered significant losses from the episode, other than perhaps a slight dent to the reputation it gained from the introduction of the original Opteron family of workstation and server chips.

“Our overall market share stayed steady throughout 2007,” said Allen. “Industry watchers expected that, because of delays to quad, we must have lost market share, but we didn’t.”

In the four-socket server space, AMD’s lead has stayed “rock solid”, according to Allen, while the single-socket business grew steadily throughout 2007. The only downturn has been in the two-socket space, which he attributed to competition from Intel’s newly introduced quad-core chips towards the end of 2007.

When it comes to explaining these figures, Allen indicated an increasing emphasis on performance per Watt among customers, plus demand for features to better support virtualisation ­ areas where AMD claims it still has a lead over the competition.

“Our advantages for energy efficiency and handling virtual workloads sustained us,” he said, but added that platform stability also played a part. For example, the quad-core parts have been designed as a drop-in replacement for AMD’s older dual-core Opteron chips, enabling customers to upgrade existing servers for greater performance if they wish, without having to worry about higher power consumption or needing extra cooling.

But AMD now faces a resurgent Intel determined to grab back any lead it might have lost. The chip giant was first to ship quad-core PC processors in 2006, and added quad-core Xeons for multi-processor systems to coincide with AMD’s Barcelona launch in 2007. Since then, Intel has introduced 45nm quad-core chips, announced a forthcoming six-core Xeon, and aims to unveil the first chips based on its Nehalem multi-core architecture by the end of this year.

Nehalem in particular appears to pose a threat to AMD’s chips in the server space. The Opteron scales well in multi-processor systems thanks to high-speed HyperTransport links that interconnect the chips, whereas Intel systems have traditionally relied on a single shared bus connecting every processor in a system to memory.

This shared bus quickly becomes a bottleneck as more processors are added, which has forced Intel to add ever-larger caches to the processor cores. But Nehalem will replace this with interconnecting links called QuickPath, while each chip gets its own pool of directly connected memory, a configuration that closely matches that of AMD’s Opteron.

“In some sense, Intel is endorsing the very architecture it has been trying to discredit for years. We see it as a validation of our position,” said Allen.

Nehalem is a threat, he added, but wondered why it has taken Intel so long to come up with QuickPath. “We had this architecture five years ago, and we have been making improvements ever since. Intel is just introducing it at the end of 2008, while we now have HyperTransport version 3, more links and DDR3 memory,” he said.

AMD’s Opteron chips still have features that the company believes will give it a competitive edge, especially in server virtualisation and power efficiency.

“Power management was not an issue for servers until a couple of years ago,” observed Allen.

The Barcelona design not only fits within the power constraints of existing Opteron chips, but each of its processor cores can be clocked down independently of the others, depending on its workload.

“We looked at ways to reduce power when the cores are under-used, so one core can run at 75 per cent of full frequency while a second is at 35 per cent, a third may be halted completely, and so on,” he said.

Barcelona also introduced a feature called Rapid Virtualisation Indexing, which boosts performance of virtual workloads by providing hardware support for mapping virtual machine memory to physical memory. The firm added this in response to requests from virtualisation software vendors, according to Allen.

Looking ahead, AMD expects to introduce its first processors manufactured using a 45nm process in the second half of the year, to be followed by eight-core chips in 2009.

The first 45nm chip is codenamed Shanghai, and will feature a 6MB L3 cache compared with the 2MB of Barcelona. It will also provide more instructions per clock cycle, but is otherwise just a slight overhaul of the Barcelona design.

Allen likened the coming update to Intel’s “tick-tock” cycle of introducing a new architecture first, then moving this to a new process technology afterwards.
Following this, Allen said he saw there would be demand for chips with cores beyond eight, especially in datacentres, and that AMD’s architecture would be able to expand to accommodate this.

“It is very clear that most server workloads are multi-tasking, not really multi-threaded,” he said, making a slight dig at Intel’s plans to make each Nehalem core capable of handling two separate threads.

AMD had a tough year in 2007, with inevitable integration issues following on from its acquisition of graphics firm ATI the previous year, and the problems with Barcelona only added to concerns that the company was losing its way. With the quad-core chips now starting to ship, AMD will be hoping that it can get back to the business of giving Intel a run for its money.